1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having an analog circuit such as, for example, microcomputers of non-contact IC card, and more particularly to a bias circuit (a constant current circuit) for generating a bias current to be flowed to the analog circuit.
2. Description of the Prior Art
FIG. 3 shows a schematic structure of a non-contact IC card. As shown in the Figure, a ROM 2a, a RAM 2b, a sending circuit 3 and a receiving circuit 4 are connected to a CPU 1, respectively. Those members construct a microcomputer 5. A data sending antenna 6 and a data receiving antenna 7 are connected to the sending circuit 3 and the receiving circuit 4 in the microcomputer 5, respectively. A battery 8 and an oscillator 9 are connected to the CPU 1, and the battery 8 is connected also to other sections. The whole IC card is sealed by a resin and the like in order to improve the tolerance for environment. The IC card is provided for sending/receiving data to and from the outside by using an electric wave. An analog circuit is necessary in the receiving circuit 4 for processing a small voltage generated in the receiving antenna 7 when the electric wave is to be received, and a bias circuit is necessary in the analog circuit for generating a bias current to be flowed into it. Since the characteristic of the analog circuit changes dependent on the bias current to be flowed, it is desirable to prevent the bias current from fluctuating dependent on the fluctuations of the power-supply voltage and the temperature as much as possible.
Referring to FIG. 4, an example of a conventional bias circuit constructed in an IC having CMOS structure will be explained hereinafter. In this case, the bias circuit is constructed in such a way that the bias current changes least in relation with the change of the power-supply voltage caused by the battery and others. In the Figure, numerals 101 and 102 indicate n channel transistors connected with a gate and drain respectively, and are connected in series. The source of the n channel transistor 101 is grounded and the drain of the n channel transistor 102 is connected to a gate of a n channel transistor 103. The source of the n channel transistor 103 is grounded, and the drain is connected to a gate and drain of a p channel transistor 104 forming a current mirror circuit and to a gate of a p channel transistor 105. A drain of the p channel transistor 105 is connected to the n channel transistors 101, 102 connected in series. Also, a gate of the p channel transistor 104 is connected also to a gate of a p channel transistor 106. The p channel transistors 104, 106 also construct a current mirror circuit, and a drain of the p channel transistor 106 is connected to the analog circuit. The two n channel transistors 101 and 102 are connected in series because it will be a mere current mirror circuit which causes unsteadiness if only one n channel transistor is provided.
In the above mentioned construction, the voltage to be added to the gate of the n channel transistor 103 is decided by the sum of two transistors of the n channel transistors 101 and 102, and the drain current of the n channel transistor 103 is decided by the gate voltage and the transistor characteristic of the n channel transistor 103. The drain current of the n channel transistor 103 is fed back to the n channel transistors 101 and 102 through the current mirror circuit, and is supplied to the analog circuit as a bias current.
Thus, the fluctuation of the bias current can be restrained despite of the fluctuation of the power-supply voltage caused by the battery 8 and others, so that the fluctuation of the characteristic of the analog circuit can be restrained.
The conventional circuit is constructed as mentioned above, and there has been a problem as described below. That is, the gate voltage of the n channel transistor 103 will depend on the sum of the temperature characteristic V.sub.TH of the n channel transistor 101 and the temperature characteristic V.sub.TH of the n channel transistor 102. The drain current of the n channel transistor 103 will depend on the difference between the temperature characteristic V.sub.TH of the gate voltage of the n channel transistor 103 and the temperature characteristic V.sub.TH of the n channel transistor 103. Thus, the drain current of the n channel transistor 103 will depend on only one temperature characteristic V.sub.TH of the n channel transistor 101, for example.
The temperature dependence of the n channel transistor 101 is explained below. The drain current of the n channel transistor 101 is given as: i.sub.D =1/2.beta.(V.sub.OS -V.sub.TH).sup.2. With the gate and drain connected, the voltage drop across the n channel transistor 101 V.sub.DS is equal to V.sub.OS, thus i.sub.D =1/2.beta.(V.sub.DS -V.sub.TH).sup.2, or ##EQU1## where V.sub.TH is a negative value for an NMOS transistor. Thus, ##EQU2## For every rise of 1.degree. C. in temperature, the magnitude of V.sub.TH decreases by about 2.5 mV. Furthermore, .beta. also decreases when temperature increases and its effect is a dominant one. Thus, V.sub.DS of the n channel transistor 101 increases when temperature rises.
The relationship between the voltage and current for a MOS transistor and its temperature characteristic described above are well know and disclosed, for example on pages 309 and 311 of Sedra et al., Microelectronic Circuits (1982), which is hereby incorporated by reference.
In order to restrain the instability of characteristics of the analog circuit, a further decrease in the temperature characteristic or temperature dependence of the bias current in the analog circuit is necessary.